One of the main drivers for package design rules is the input/output (I/O) density per mm per layer (IO/mm/layer). The I/O density may be limited by the via pad sizes. However, current packaging technologies limit the extent to which the size of the via pads may be reduced. The via pads need to be relatively large due to the laser drilling process used to create the via openings through a dielectric layer above the via pads. Laser drilling is limited by the minimum feature size and the misalignment of the laser when drilling the via opening. For example, the minimum feature size of a laser drilled via opening may be approximately 40 μm or larger when a CO2 laser is used, and the misalignment between the layers may be approximately +/−15 μm or larger. As such, the via pad sizes may need to be approximately 70 μm (i.e., 40+2(15) μm) or larger. Alternative laser sources, such as UV lasers, may be able to reduce the via opening more, but throughput is also greatly decreased.
FIG. 1 is a plan view illustration of a portion of an interconnect layer in a package that illustrates the problem with large pad sizes. In FIG. 1, two conductive lines 130 are formed between the two pads 110. A via 120 is formed on the surface of each pad 110. For simplicity, the dielectric layer through which the vias 120 are formed is omitted. The large diameter of the pads 110 that is needed to allow for a large via 120 and any misalignment, prevents adding more conductive lines 130 between the pads 110. Accordingly, the effective routing density on package layers may be less than 30 IO/mm when laser drilling is used to form the vias. This routing density is not sufficient for some packages, such as server/high-performance computing (HPC) packages. Currently, in order to provide sufficient escape routing density, more expensive technologies need to be used, such as silicon interposers and embedded silicon bridges.
Silicon interposers achieve high routing density because of the design rules available on silicon allowing for significantly reduced line widths and spacing. The use of silicon interposers allows for the vias to be lithographically defined instead of laser drilled. This allows for small vias and misalignment during via formation that may be approximately 1 μm or less. However, silicon interposers are expensive, especially if used for large dies such as server/HPC dies. Often silicon interposers also have a maximum size (e.g., 22 mm×33 mm due to the reticle size used in silicon processing) that is too small for more advanced applications.
The use of embedded silicon bridges has also been proposed as a cheaper alternative to very large silicon interposers. However, the addition of embedding a silicon bridge in the package is more expensive than a purely organic package stack-up.
Thus, improvements are needed in the area of via manufacturing technologies.